Modeling and Simulation of High-Speed Links & Interconnects

Modeling and Simulation of High-Speed Links & Interconnects

38 38 people viewed this event.
Overview

This webinar aims to streamline the system design and analysis process, enabling participants to efficiently transition from initial SerDes system floor planning to detailed system design and robust signal integrity analysis. By focusing on practical, tool-driven methodologies, the webinar seeks to empower engineers to overcome common pitfalls in system design, ensuring high-performance, reliable communication systems in an era of ever-increasing data rate requirements.

Highlights
  • SerDes floor planning with SerDes Designer App
  • Detailed SerDes design and IBIS-AMI generation with Simulink
  • Comprehensive signal integrity simulation and analysis
About the Presenter

Jahnavi Dhulipala | Senior Application Engineer| MathWorks

Jahnavi Dhulipala is a senior application engineer at MathWorks and is based in Bangalore. She specializes in RF, analog, and mixed-signal component and system design and works with tier-1 semiconductor and electronics companies to help support their adoption and success with top-down and model-driven system design and verification workflows.

 

Date And Time

27-06-2025 - 01:30 PM (+04) to
27-06-2025 - 02:30 PM (+04)
 

Registration End Date

27-06-2025
 

Location

Online event
 

Event Category

Share With Friends

Scroll to Top
Computational Enterprise Simulations
Privacy Overview

This website uses cookies so that we can provide you with the best user experience possible. Cookie information is stored in your browser and performs functions such as recognising you when you return to our website and helping our team to understand which sections of the website you find most interesting and useful.