Filter Design HDL Coder
Filter Design HDL Coder generates synthesizable, portable VHDL® and Verilog® code for implementing fixed-point filters designed with MATLAB on FPGAs or ASICs. It automatically creates VHDL and Verilog test benches for simulating, testing, and verifying the generated code.
Working with Filter Design HDL Coder
Filter Design HDL Coder is integrated with DSP System Toolbox to provide a unified design and implementation environment. You can design filters and generate VHDL and Verilog code either from the MATLAB command line or from DSP System Toolbox using the Filter Designer app or the Filter Builder app.
Designing Fixed-Point Filters
The design entry input to Filter Design HDL Coder is a quantized filter that you create in one of two ways:
- Design and quantize the filter with DSP System Toolbox
- Design the filter with Signal Processing Toolbox and then quantize it with DSP System Toolbox
Optimizing Filter Architecture
Filter Design HDL Coder optimizes filter architecture by automatically mapping your design to efficient hardware structures, such as systolic or transposed forms. It reduces resource usage through techniques like multiplier sharing and pipelining, and supports HDL-specific optimizations to meet area, speed, and latency requirements.
Generating HDL for Fixed-Point Filters
You can generate VHDL or Verilog code for fixed-point filters from either the Filter Designer app or the Filter Builder app. When generating HDL code from either app, you can set HDL generation options to specify the implementation architecture, select port data types, insert pipeline registers, and more. Other options let you generate and configure a test bench for your filter HDL design.
Customizing VHDL and Verilog Code
Filter Design HDL Coder generates filter and test bench HDL code for a quantized filter using option settings or property name/value pairs. These settings allow you to name language elements, set port parameters, and enable advanced HDL features. All properties have defaults, but you can customize them using the Filter Design and Analysis app or the Filter Builder app.
Testing and Synthesizing Generated HDL Code
You can create a VHDL or Verilog test bench to simulate and test the generated HDL code. With HDL Verifier, you can also generate a Simulink cosimulation block to link your Simulink-based filter model with the HDL running in Cadence® or Mentor® simulators. This allows you to compare HDL results with the behavioral model directly and use MATLAB and Simulink tools to test, debug, and verify your filter design.
