Vision HDL Toolbox
Vision HDL Toolbox provides pixel-streaming algorithms for designing and implementing vision systems on FPGAs and ASICs. It supports various interface types, frame sizes, and frame rates, ensuring flexibility for different applications. The toolbox includes image processing, video, and computer vision algorithms optimized for HDL implementation, generating readable and synthesizable VHDL and Verilog code with HDL Coder. The generated code is FPGA-proven for resolutions up to 8K and high frame rate (HFR) video. Toolbox capabilities are accessible through MATLAB functions, System objects, and Simulink blocks.
Use HDL-Optimized Vision Algorithm Blocks
Select hardware-optimized streaming-pixel blocks for image and vision processing. Implement on FPGAs, ASICs, and SoCs.
Perform Pixel-Streaming Design
Process 4K/8K videos with pixel control, ROI, and line buffers. Design and simulate efficient hardware using single or multipixel streaming for vision algorithms.
Get Started with Reference Vision Applications
Customize hardware-proven reference subsystems for efficient computer vision applications like automated driving, object detection, and camera pipelines.
Model External Memory Interfaces
Model AXI external memory and frame buffer in Simulink for pixel streaming. Integrate processor memory access in HW/SW codesign and deploy using SoC Blockset.
Integrate Deep Learning in Vision- Based FPGA Design
Deploy YOLO v2 on Zynq hardware for object detection using pre-built reference designs with live or captured camera input.
Prototype and Verify on FPGAs and SoCs
Prototype live video design on AMD Zynq, generate VHDL/Verilog with HDL Coder, and verify with HDL Verifier.